1. Technical Field
The present invention relates to component packaging and finds particular application in wafer-level packaging of, for example, electrical and/or optical components such as lasers and associated devices.
2. Related Art
Component packaging is used in semiconductor-based technologies generally to protect or support a component or an assembly of components for handling or further processing. Packaging can potentially be done at different levels, from individual items up to finished assemblies. For instance, a sub-assembly of components can be packaged together so that a function of the sub-assembly can be tested without waiting for the finished equipment.
Various types of protection can be offered by packaging, including mechanical and chemical. For example, a passivation layer can be used to provide environmental protection for any active and passive components integrated on a substrate. Such a passivation layer can be provided during an assembly process, as an intermediate layer of a wafer level assembly, or deposited as a final step in wafer level processing. In another example, a planarisation layer can be used to improve a surface for subsequent layers or devices. Planarisation layers are used for example to smooth the surface of a substrate which is otherwise uneven, such as ceramic and composite surfaces such as alumina and LTCC substrates or plastics. Unpolished substrate surfaces can be planarised to achieve good surface quality and surfaces already carrying other structures, such as interconnect material, can be smoothed over by a planarisation layer to present a flat surface in spite of the presence of the structures.
Wafer level packaging is becoming known as an attractive method of packaging low to mid density devices for several reasons: cost, size and ease of testing.
Cost is the largest force driving wafer-level packaging. Using simultaneous batch integration processing, an entire wafer or substrate can be packaged instead of packaging each device. Wafer level packaging reduces the number of steps involved in packaging, potentially eliminates the use of underfill and allows for centralized processing during fabrication. Further, packaging of the wafer allows for a high degree of process integration, due to the use of technologies such as thin film and lithography, which decreases cost. Centralized packaging during fabrication also reduces packaging time and inventory, since devices are no longer packaged separately prior to assembly.
Device size is also a driving force for wafer-level packaging. The size of a wafer level packaged device can be much the same as packaged semiconductor chips.
From the testing point of view, wafer-level packaging has a major advantage. Testing at the wafer-level (which is intermediate testing of the device functionality to decide which particular devices are going to be finally packaged and used as an end product) can reduce test costs by as much as 50%, requiring both less capital and reducing the number of test steps.
However, known wafer-level packaging is not suitable for use in the fabrication, assembly and packaging of all components and devices. For example, it is not used for active optical devices and components such as tunable and/or external cavity lasers.
Conventional approaches for wafer level integration and the fabrication of “build-up layers” on an integration substrate are based on the deposition and patterning of organic materials such as Dow Chemical's SilK, or the chemical vapour deposition (CVD) of metal oxide type coatings.
A known problem of purely organic materials is that their co-efficient of thermal expansion (CTE) is high compared to that of materials such as metals and semiconductors used in substrate-based integration for example for interconnects and other aspects of optoelectronic operations. A typical CTE of organic materials is 60 ppm (parts per million per ° C.) or higher. A significant mismatch in CTE between a layer and material it is in contact with tends to cause stresses at the interface. In addition, organic materials lack thermal stability, which may limit a device's long-term stability and exclude some manufacturing techniques such as soldering and metallization.
On the other hand, CVD is a high temperature process, which limits the selection of substrate materials and the type of electronic or optoelectronic devices which can be assembled to the substrate before CVD inorganic film deposition. Furthermore, the processing of openings (assembly holes) is time consuming and deep structures are relatively complicated to fabricate.